Design of an 8 Points 1-D IDCT of the Emerging HEVC Video Coding Standard

This work presents the design implementation of a 8points 1-D IDCT used in the emerging video coding standard HEVC – High Efficiency Video Coding. The 8-points 1-D IDCT is used in the 8x8 2-D IDCT of the HEVC standard. The IDCT is performed by the video encoder and decoder as well. The hardware design implementation was done in order to enable real time video coding processing. The architecture was designed in a combinational way and multiplierless as well. Results were obtained using VHDL language and the target device was an Stratix V family FPGA. Based on the synthesis results, it was possible to achieve 960 Msamples/s and the implemented architecture – even being purely combinational – is capable to process more than 30 QFHD (3840x2160 pixels) frames per second. Keywords— HEVC, IDCT, Video Coding, Hardware Implementation, Multiplierless